1. Field of the Invention
The present invention relates to a plasma display panel (hereinafter referred to as a PDP) and a method of driving the same.
A PDP is developed as a display device having a large screen. A 25-inch high definition monitor and a 60-inch TV set using the PDP have been put into practical use. A larger screen is required in the market, and techniques for satisfying the requirement are under development.
2. Description of the Prior Art
In a conventional AC type PDP display, cells arranged in a matrix are addressed in a linear sequential scanning format, in which an appropriate quantity of wall charge is formed only in cells to be lighted, and then the wall charge is used for generating display discharge at plural times corresponding to display gradation. An addressing period is proportional to the number of rows of a display screen (i.e., resolution in the vertical direction). Therefore, the higher the resolution is, the shorter the period that can be assigned to the display discharge in a frame period becomes. In addition, the number of division that a frame can be divided into for a gradation display decreases. In other words, it is difficult to realize high luminance and a large number of gradation steps in a high resolution PDP.
Conventionally, as a technique for shortening an addressing period, a “dual scan” method is known, in which a display screen 80 is divided into two areas vertically as shown in FIG. 20A, and two display areas 81 and 82 are addressed concurrently. Each data electrode is divided as a result of the division of the display screen 80, and column selection in the display area 81 or 82 is performed by the data electrode D1 or D2 corresponding to each display area 81 or 82. Since two rows are selected simultaneously in the dual scan, the addressing period is a half of that in the single scan in which only one row is selected at one time. Japanese unexamined patent publication No. 11-312471 discloses a technique in which the display screen 90 is divided into four areas as shown in FIG. 20B. In this technique, data electrodes D12 and D22 in display areas 92 and 93 located in the middle in the vertical direction are led out of the display screen 90 via display areas 91 and 94 located in the end portions so as to be connected with a driving circuit. In the display areas 91 and 94, data electrodes D11 and D21 are located so that an address discharge is generated between a data electrode and a scan electrode, while the data electrodes D12 and D22 are insulated by a partition 290 that defines discharge spaces so that a discharge is not generated. By dividing the display screen 90 into four areas, the addressing period can be shortened to one fourth.
According to the conventional technique of dividing data electrodes within the display screen, there are many rows that cannot be selected at the same time between the rows that can be selected simultaneously. For example, if a display screen having 1024 rows is divided into two areas by the dual scan, there are 511 (=1024/2−1) rows between the first rows of two display areas 81 and 82. In order to electrically connect scan electrodes corresponding to rows that can be selected simultaneously so as to reduce components of the driving circuit, multilayered wiring is required for crossing many scan electrodes. A rise in cost is inescapable when the multilayered wiring is used in any portion of a substrate constituting the PDP, a wiring cable connecting the PDP with a driving circuit board, and a driving circuit board.
Moreover, only one end of the data electrode is led out of the display screen. Therefore, if a data electrode breaks, cells that are located closer to the middle portion than the broken portion become unable to be controlled.